PDB Test Plan & Test Results

Owned by Logan Hartford
Last updated: Jan 15, 2023
4 min read

Footprint Issues:

  • The reset switch is always shorting RST pin to GND on STM

  • The Inductor footprint is way too small

  • MOSFET footprint issue from rev3

Post-Assembly

Check all required components are assembled and DNP components are not assembled
Verify components oriented correctly (polarity, pin 1 designators, etc.)
Verify there are no bridges between parts/pins creating unwanted shorts
Verify general soldering quality - no stray solder, burns, etc., all pins and pads connected with enough solder

Unpowered Tests

Verify power rails are not shorted to GND or with each other
Verify EN/RST/SHDN pins are not shorted to either GND or a power rail, unless it is supposed to be
Verify communication protocol lines (i.e. SDA & SCL for I2C, MISO MOSI SCLK & CS for SPI, etc.) are not shorted with each other, with a power rail, or GND

If any shorts are found, do not connect the board to a power supply. Locate and attempt to fix the cause of any shorts before continuing.

Basic Powered Tests

General Tests:

Power on board + touch test, verify components and the board itself does not get too hot
Probe power rails, verify correct voltage
Verify all ICs, components, LEDs, etc. are powered on successfully. Communicate with all peripherals
Program microcontroller

48V-5V buck converter & 48V-17V buck converter:

Enable conditions function as expected
Verify output current limit
Verify output voltage limit

5V smart high-side switches:

Verify enable condition
Verify output current limit

17V high-side switch:

Verify enable condition

 

Performance Tests

48V-5V buck converter & 48V-17V buck converter

17V Buck

Test Data: PDB Testing 17V Buck.xlsx

  • The output voltage drops when the buck is under a light load and the input voltage is reduced

    • The effect is less and less as more load is applied until 2A when it is able to maintain the output voltage across the entire expected input voltage

  • The Schematic says 4A max but the output does not shut down when a 4A+ load is applied.

    • I was able to get 4.5A out if it with not signs of the shutdown, I stopped going up because I didn’t want to fry anything

    • Based on Rsense selection, it looks like max current limit is set to 8.5 amps

  • The buck cannot handle large transient loads

    • Above a 1A transient, the output voltage is dropped significantly and never recovers.

    • EX when going from 0.1-4A it dropped the output to 12.5V and never recovered

  • The transient issue and the Undervoltage during light loads issue were both solved by disabling the burst mode

    • Can handle large transients fine now

  • The 17V will not come up if you start it with a load on the output which is bad

    • Need to resolve this

  • Should add more caps and optimize the hot loop a bit

  • Should add the ability to enable and disable the buck with the STM

 

5V Buck

Test Data: PDB Testing 5V.xlsx

  • Very noisy output

    • Noise at input of inductor, propagates through the board

    • Could lower the switching freq -wolfy

  • Voltage drops about 0.1 V from 0A to 1.9A at the output

  • Current limit works

  • Good line regulation

  • Need to test if the load switches can shutdown the output

    • They do

  • Can’t measure transients or ripple because there is massive noise at the output like +/-10V

    • Cant trigger

    • Can jump from 0-1.9 but only at high input voltage

  • 5V regulator is current limited to 2A right now and it should be 10A

    • Bases on Rsense selection, the max current is set to 2A

    • Should swap out the resistor and see how high it can go before it claps out

  • Should add more caps and optimize the hot loop a bit

  • Should add the ability to enable and disable the buck with the STM

 

17V Actions Items:

Offline 17V Tasks:

5V Actions Items:

Offline 5V Tasks:

 

 

Rev 4.1 additions

More vias vias stitch everything

GND COMMON LAYER, TOP AND BOTTOM

Minimize Current return paths, EMI is an issue on this board, 8-12 V_pp on 48V line

 

Redesign layout of the Buck converters prioritizing the output capacitor placement close to return of the lowside N-fet,

Spec parts for higher voltage tolerance

MORE VIAS In GND

CTL lines away from the inductor

Thicker gate lines that are short – minimize the inductance on the line