Rev 4 PDB PCB Layout Review

Owned by Rishith Bomman
Last updated: Oct 06, 2022
12 min read

 

Design-For-Manufacture (JLCPCB) (@Wolfgang Windholtz (Deactivated) )

Ensures the PCB layout is in line with the capabilities of JLCPCB. If the board will be manufactured elsewhere, this section should be modified to fit the manufacturer’s capabilities. The capabilities of JLCPCB are listed here: https://jlcpcb.com/capabilities/Capabilities

When reviewing this section, instead of checking everywhere on the board, just make sure the design rules match what is on the manufacturer’s website, and the Design Rule Check reports no violations. Ensure the following sections are OK in the design rules:

Drill/hole size
Minimum annular ring
Minimum clearance
Minimum trace width and spacing
Solder mask

General Guidelines (@Logan Hartford)

General things to be aware of when reviewing the layout.

Decoupling capacitors are placed as close as possible to the parts they are decoupling. If multiple caps are used, place them closest from smallest capacitance to largest capacitance
No polygons are shelved, and all are repoured
No dead copper from any polygons
Thermal reliefs used for all parts, except for parts carrying high amounts of current - allows for easier rework
0805 components and smaller have copper balancing (copper connected to one pad is less than 2x the copper connected to the other pad) - this helps prevent tombstoning while soldering
No traces routed underneath inductors, unless it is on a different layer with a GND plane in between
Do not place small components (i.e. chip resistors/capacitors) next to very tall components (i.e. connectors) - make at least 1mm of space
Double check mounting holes are included if necessary (work with mech. team to determine if they are wanted)
No components underneath other components (check 3D body clearance in 3D view)
Ensure 0.5mm clearance from all mounting holes (set this up in your design rules)

Logan’s Comments:

  • Decoupling

    • Decoupling caps for SW2 and SW3 couple be placed closer

    • Smallest capacitance should be placed closest to the pin, reverser the order of these two - done

    • You haven’t connected the decoupling caps to the pins they are intended to decouple here - aren’t they connected to the power planes

  • Polygon Dead Copper - done

    • A bunch of your polygon pours on the top layer don’t have this turned on however, they are small, simple shapes so it won’t matter much. Your layer 3 GND pour doesn’t have it enabled either.

  • Thermal Reliefs

    • I don’t see any thermal reliefs on this board. Most of this board is involved in power so using thermal reliefs would be a laborious case-by-case basis. Most of the components that would benefit from thermal reliefs are decoupling caps which are unlikely to be reworked so it may not be worth going through the trouble of adding them. Talk to Farris about this and get his thoughts. - Talk to Farris

  • Copper balancing

    • Due to the fact that there are no thermal reliefs on this board, copper balancing will be an issue for all of the resistors and caps which have 1 pin connected to a polygon pour. Adding thermal reliefs to these components may be worth it. Don’t add thermal reliefs to any components which are carrying high power though even if copper balancing is an issue. Some examples of components that would be good candidates for thermal reliefs are C40, C53, and R1. - Talk to Farris

  • Mounting hole clearance - done

    • Depending on what type of fasteners are used to mount the board, these holes may not have enough clearance. I would give the holes more space if it is not too difficult.

  • Where is the 3D body for this component? - done but what is the USB port even for?

Silkscreen (@Logan Hartford )

All silkscreen is TrueType Arial font, with a minimum text height of 50mil
Text block that includes the board name, revision, designer name(s), and completion date (month and year) is included on the silkscreen
UW Robotics Team logo is included on the silkscreen
No vias over silkscreen
No silkscreen under components or over exposed copper (i.e. pads)
All components have their designators visible on the silkscreen
Check that all vias are tented

  • True type Arial font

    • There are a bunch that are not in the right font. Fix this quickly by selecting a text object, right clicking>Find similar objects>OK. This will select all the text on the board. Then set the font to TrueType Arial in the properties window and you will update all the text simultaneously - done

  • Text block needs to be updated - done

  • Need to add the UWRT robotics logo to the board - ask how

  • Component designators

    • These should be rotated done

    • Move this one - done

    • Too big - done

    • Text width to thick - done

    • Here as well - done

    • To thick here as well - done

    • give the board a once over and see if you can find any other designators that don't seem to match the others - done

    • Some of your vias are not tented. You can quickly tent all of them using the method described above for changing the text font - done

 

Routing & Pours (@Wolfgang Windholtz (Deactivated))

Avoid overlapping polygons. Overlapping polygons of the same net should be merged into one
No angles < 45 degrees
Traces are routed without any acute angles. Avoid 90 degree angles as well if possible
Differential signals are routed properly with length-matching
For signals with controlled impedance, trace width and spacing are calculated using an impedance calculator
If going with JLCPCB, use their Impedance Calculator
When moving high-speed/differential signals between layers, surround the vias with GND vias

Farris’s comments:

  • Keep the GND connection to the GND plane as short as possible

    • For small pads, use a relatively wide trace (i.e. 15-20mil) with a via close by. Avoid doing longer traces like these - done

    • For larger pads, use a wide pour with a couple GND vias next to/around the pad. C301 is a good example of this - done

    • However, connections similar to C201 could be improved - done

    • Wolfgangs Comments:

      • GND the bottom layer - don’t get it

Connectors (@Ari Wasch)

 

Verify enough space around connectors for mating
Double check pinout will match destination connector - be especially careful here, as the pinout may need to reversed if the connectors are facing different directions
Connector purpose and pinout (if necessary) is detailed in the silkscreen

Design-for-Test (Rayyan + @Logan Hartford + @Ari Wasch + other in person people?)

  • Add test points for CAN

  • Add another GND test-point

  • Add test points for MCU enable

Specific Layout Sections for Review

Reverse polarity circuit (@Farris Matar )

  • D2 and Q1 are overlapping, they won’t be able to be assembled like this. Rearrange the components to make room - done

  • Delete these ON OFF texts - done

  • Plenty of copper to support the required current, nice work, no other issues to fix here - done

  • Unrelated to the reverse polarity circuit, but let’s move the VBAT_FUSED connectors so they aren’t so cramped. Extend the pour up to the top here, this will allow MUCH more copper for these connections. Be sure to also add VBAT_OUT and GND texts on the silkscreen next to the pins of each connector, similar to the VBAT_IN connector - Done

  •  

17V buck (@Logan Hartford)

Logans Comments:

Most of my comments are coming from reading the Applications Information section (pg. 20) of the IC data sheet

  • Hot Loop

    • In this circuit, the input capacitors is the only component that is a part of the hot loop. This means you want to minimize the distance between C201 and Q201. Right now they are pretty far away and could probably be placed closer - done

    • The datasheet also recommends connecting the source of the lowside fet directly to the GND of the input capacitor for the best hot loop performance - talk to Farris

    • Based on this I think a better place for the input cap would be - done

  • SGND and PGND

    • From what I can tell, you have done a good job of keeping the signal and power GNDs separate. However, it might be worth including a cap across the synchronous switch to prevent any potential corruption of the SGND. - talk to Farris

    • If we don’t end up needing it then it can be left as a blank pad but I think it is better to have it and not neet it then need it and not have it. - Talk to Farris

  • Decoupling caps

    • In the datasheet, it says to place the VCC and BOOST decoupling caps close to the IC

    • These caps should be moved closer to the IC - Hard to do without interference from 17 V rail

  • Feedback

    • The datasheet recommends connecting the feedback resistor directly to the terminals of the output caps. It also recommends placing the FB resistors close to the IC.

    • In the current layout, it is impossible to do these two things. I would suggest moving the IC and input cap in order to meet these requirements - done

    • Talk with @Farris Matar about this and see what he thinks about these changes

  • CS+/-

    • Moving the IC would also help with this - done

5V buck (@Logan Hartford )

The 5V buck layout suffers from many of the same issues as the 17V buck so I’ll only briefly list them here. In this case, making the changes would result in a much more significant redesign of the board. I will leave it to @Rishith Bomman and @Farris Matar ‘s discretion to determine if these changes are worth making. If we need to extend the deadline that’s fine. If the board shows up and doesn’t work that will be much worse.

  • PGND and SGND

    • I think the PGND and SGND separation should be improved here. Right now the noisey GND of the input capacitor is right next to the small signal side of the IC. Moving the input capacitor could improve this. - Talk to Farris

    • This applies here as well - Talk to Farris

  • Hot Loop - Talk to Farris

    • Hot loop layout could be improved by making the change suggested above

  • Feedback - Talk to Farris

    • In order to apply the feedback layout recommendations in the datasheet, a significant change in the design would need to be made, I’ll give a rough Idea of how this could be done but it would be quite a lot of work

    • Approximate placement - Talk to Farris

  • This is by no means optimized, I just did this quickly as an example. As I said, it will be up to you and Farris to decide if this is worth it or not

Microcontroller( @Ari Wasch + Rayyan)

make sure that decoupling capacitors are as close as possible to ICs - done

C60 should be placed as close as possible to U700. also why is it U700? that seems very high. - following a naming convention based on the sheet number - done

 

Make sure all the decoupling capacitors for the ICs are as close as possible to the pins in the IC. - done

CAN/RS422( @Ari Wasch + Rayyan)

Load switches. (@Farris Matar + @Wolfgang Windholtz (Deactivated) )

Farris’s Comments:

  • 17V load switch:

    • Could extend the 17V_LOAD pour down the right side here, just to add some more copper - done

    • Also, move the R77 designator to the right of the part, to match the other resistor - done

  • 5V load switches:

    • Could move this via further to the right to reduce the gap in the 5V pour - done

    • Rename the “TP 5VL” testpoints to EN1, EN2, etc. so it’s clearer what the testpoints are for

Wolfgang Comments:

Move C39-41 Capacitors closer to input - Done