This page is meant to provide a list of things that should be checked when reviewing the layout for a PCB. It is the designer’s responsibility to check for ALL of the things below themselves, then assign others to review their layout and ensure the changes required are made before sending the board off to be fabricated.

Generic Layout Review Sections

Design-For-Manufacture (JLCPCB) (@Logan Hartford & Billy)

Ensures the PCB layout is in line with the capabilities of JLCPCB. If the board will be manufactured elsewhere, this section should be modified to fit the manufacturer’s capabilities. The capabilities of JLCPCB are listed here: PCB Manufacturing & Assembly Capabilities - JLCPCB

When reviewing this section, instead of checking everywhere on the board, just make sure the design rules match what is on the manufacturer’s website, and the Design Rule Check reports no violations. Ensure the following sections are OK in the design rules:

• See Farris’s comments about hole clearance and board outline clearance

General Guidelines (@Farris Matar & Jack)

General things to be aware of when reviewing the layout.

Farris’s comments:

• Decoupling caps look great, no issues there

• For your GND pours on the top and bottom layers, select the Remove Dead Copper option to get rid of all the floating copper islands that aren’t actually connected to GND. Also, increase the Remove Necks Less Than to 15mil

Open

• Thicken the thermal reliefs from J3 (VBAT connector, could have high current consumption) and remove thermal reliefs on U6

  • To edit the thermal reliefs, select the pad(s), check the Thermal Reliefs box and click the 3 dots, then update the values to be much larger. To remove the thermal reliefs, Change the Connect Style drop down to Direct Connect

Open

• Copper balancing should be OK, since you have thermal reliefs on all those components

• Add 0.5mm clearance for your mounting holes - go to Design > Rules, expand the Electrical group, expand Clearance and select the Clearance rule, then change the Hole clearance to 0.5mm

• Remove thermal reliefs from vias (In design rules, go to Plane > Polygon Connect Style > PolygonConnect, select Advanced, scroll to Via Connection and select Direct Connect)

• Add 1mm clearance from your board outline - In design rules, expand Manufacturing, expand Board Outline Clearance and select the Board Outline Clearance rule, then change all values in the table to 1mm

• Don’t forget to rerun the Design Rule check for your board after updating the design rules, just to make sure no new violations appeared

• Add via stitching for your GND pours on the top and bottom layers (Tools > Via Stitching/Shielding > Add Stitching to Net)

  • Use 12 mil hole, 24 mil diameter vias. A 250 mil grid should add enough vias. The via stitching might place vias on pads/components for some reason, so be sure to run the design rule check and delete any vias causing shorts

• Tent all your vias (select all vias on the board, under Solder Mask Expansion click Manual and check the Tented boxes)

Logans Comments:

• For your top and bottom GND pours, you can generate the polygons based on the board outline rather than drawing them like this

• Once the rest of the layout changes have been made, add tear drops to you traces: Tools>Teardrops>

• Fix this trace

Silkscreen (@Ari Wasch & Olivia)

Routing & Pours (@Wolfgang Windholtz (Deactivated) & Rayaan)

Connectors (@Logan Hartford & Billy)

• could add a label to the balancing connector

I think connector needs to be against the edge so male connector fits - could be wrong though

Design-for-Test (@Farris Matar & Jack)

Farris’s comments:

• Plenty of testpoints and an LED for 3.3V power rail

• My only comment is to add more GND testpoints and distribute them around the board. I suggest using the TESTPOINT_SMD_LOOP from our library, as it’s very easy to use with the oscilloscope and DMM probes

Specific Layout Sections for Review {everyone?}

Farris’s Comments:

I reviewed the buck converter & CAN transceiver layouts. Can we have the BMS, STM32 and LED display each reviewed by 1 or 2 people?

• Buck converter layout:

  • Move C32 next to the output of your buck converter - this is supposed to be your output capacitor, so it needs to be close to the buck output

  • Add more vias from 3.3V to your power plane. This is best done by adding a pour near your buck output/output capacitor and adding a bunch of vias there

  • Use a large, thick copper pour for the OUT net of the IC (NetD2_2), as well as the 3V3 connections.

  • Do not route the 3V3 connection to pin 4 of U6 on the top layer, this is your FB trace which is a very sensitive analog signal, routing it under the inductor will cause a lot of interference issues and make the output voltage unstable. Instead, route a trace from the inductor output down to the bottom layer with a via, then route it to the buck IC and bring it back up using a via next to the pad

  • Careful, you have a lot of blind 3.3V vias, which will make building this board much more expensive. Select all blind (1-3) vias and change them to Thru (1-4) vias

• CAN Transceiver:

  • You need to route the CAN signals as differential pairs and with 120 ohms controlled impedance. Check out my high speed layout tutorial here 4.2 Signal Integrity & High Speed Layout Tutorial, if you start watching from 46:45, I explain how to set up and do proper differential pair routing with controlled impedance in Altium. If you’re interested in the theory and reasoning for why this is important, start watching from 33:20

    • You’ll probably need to reorient and/or rearrange components to make it possible to route the differential pairs. See the PDB layout for a good example of how to place the components to make it easy

Logan’s Comments

• STM32 Layout

  • For the crystal oscillator, you should have the crystal as close to the input/output pins as possible. The caps should also be right up against the oscillator

  • Try to avoid creating acute angles

• LED Display

  • I can’t think of or find any additional layout requirement. It seems good to me.

• BMS

  • Parasitic capacitance can result in errors charge injection errors

  • Here is how they did they layout for the EVAL board

  • It looks pretty similar to ours but I am not very familiar with how to minimize parasitic capacitance. Can someone with more experience in this area review this section please.

  • This is not best practice, better to pull the trace out and away from the pads. Doing it this way encourages solder bridges. For this IC packages, that is not a big deal but for DFN or QFN, this can cause the IC to mount at an angle or twist due to the uneven distribution of solder.

  • Try to avoid creating acute angles

Ari’s comments:

Get rid of 90 degree trace. make 2 traces coming out of the Pad of R3

Move trace down on NetU2 to avoid acute angels

connect everything through a pad rather than connecting everything through the middle of a trace

Have a polygon pour for VBAT on the power layer. connect through many vias and with smaller polygon pours on the first layer.

Trace is too small to draw enough current from the battery. Confirm to make sure that Cell12 is the same as VBAT (use a multi-meter and test continuity on the battery). If it is the same (which it should be), make that power terminal connected to VBAT instead of CELL12. also make the VBAT connection come from VBAT on the power layer.

Add top level polygon pour for 3.3V with many vias connecting to the power layer for better connectivity.

There's no polygons in the middle layers. one layer should be all GND, and another layer should have a large polygon in the middle for VBAT and the rest should be 3.3V. I don't think 3.3V vias connect to anything right now.

because you have the 3.3v polygon pour, you don't need the trace

Make VBAT pour a little thicker

Make the 3.3v polygon go through the top of the board. the left side of the 3.3V is kind of isolated

Wolfgang’s Comment:

Your circuit looks good nothing extremely wrong as long as you fix your grounding. PUT MORE GND VIAS

read the following article: https://www.allaboutcircuits.com/technical-articles/techniques-dc-dc-buck-converter-PCB-layout/

NetD2_2 needs to be much thicker it is your output to the inductor.

Your switching loops are large think about ways of positioning components to make them tighter, The IC does not need to be on the edge.

MORE GND VIAS EVERYWHERE. there should be minimum 4 but put like 10 for these big plates. the diode needs like 8.

Move C32 closer to the output of the inductor.

Move C7 to the buzzer circuit

Switch the orientation of the input connector maybe. put the input capacitors close to the connector.

could scoot the CAN and Input over giving more room for a better buck converter layout

This is optimistic but an idea about loops