MarsRoverHardware/Projects/24V Multiphase Buck/Rev 2 at master · uwrobotics/MarsRoverHardware

Datasheet Calculations

Formulas used: Datasheet Calculations.docx

Calculations used: https://uofwaterloo-my.sharepoint.com/:x:/g/personal/laphartf_uwaterloo_ca/EXZmLZJsgfhKl3uAZ2ZXCosBsq3ntQcYzEnib-hCZegW1w?e=pE0gwM

24V Multiphase Buck.SchDoc (Rishith)

Comments:

Open

is there a reason that the decoupling capacitors are connected to the current sensing port, or can this be separated on the page

24V Multiphase Buck.SchDoc (Josh)

Comments:

24V Multiphase Buck.SchDoc (Ari)

Please focus on the Peak Current Limit Programming and Current Sensing sections of the datasheet calculations

Comments:

For current sensing calculations, I got 0.0026 Ohms, but i’m not sure if that's correct.

should we be calculating the MIN or the MAX for this equation? Because RSENSE takes the m

ax. Also what VCS value are you supposed to use. on the calculation sheet, there is a min and max

Response: We are not too concerned with having an exact value for Rsense, we decided to use 0.005 Ohm as it it an easier resistor value to work with and won’t affect the further calculations as drastically

Open

COMP1 and COMP2 values for resistor and capacitors don't match calculations in the calculation sheet

Response: These were updated on the new schematic.

PIN2 RRT Value might be wrong. I calculated (295693+133)/8.8 = 33601 ohms

Response: Yes your suppose to use 133000

This only regulates the output. it will shut off if less than 24 volts. don't you want to regulate the input?

24V Multiphase Buck.SchDoc (Farris)

Comments on component values and part selection:

• For your inductor, I would reduce the peak-to-peak current ripple to 20% instead of 30%, due to how much current is going through the inductor. This will help reduce losses from the inductor. I’d also select an inductance that is equal to or higher than the calculated inductance value, instead of below

• IC Internal Power Dissipation: Note that for this equation, Qgate is the sum of the gate charge for BOTH high and low-side FETs of BOTH controllers, in other words every single FET’s gate charge is summed up in this equation. This means 8 total FETs for a double FET config, and 4 total FETs for a single FET config.

  • Currently, you’re counting only 4 total FETs for a double FET config and 2 total FETs for a single FET config, so your calculated values for power dissipation are half of the actual values

  • It also means that currently your internal power dissipation is way too high, even for the single FET config. Couple ways to solve this:

    • Reduce your switching frequency, maybe down to 200kHz. This reduces the power dissipation by almost 45%

      • Be careful of the other component values that this will change, mostly just a bunch of resistors and ceramic capacitors that will need adjusting

    • Find a FET with lower gate charge (even just slightly lower will help a lot as it gets compounded 4 or 8 times)

      • This might be good if going with the double FET config https://www.digikey.ca/en/products/detail/micro-commercial-co/MCAC60N10Y-TP/15652824. It’s not as high specs as the current FET, but has almost half the gate charge

    • Reduce the voltage at the VCCEXT pin (see comment under general comments)

  • We should aim to keep the internal power dissipation at 2W or lower

• For your bootstrap capacitors, remember you need to sum the gate charge for 2 FETs, not just one, if going with the double-FET config

General comments:

• Careful, the GND port on R2 isn’t connected properly; Altium currently sees it as floating

• Seems the current limit was reduced from 17.5A to 15.5A, why is this?

• I recommend adding a voltage divider to the 24V on the VCCEXT pin, as with the ripple on the 24V it will go over the 24V limit on the VCCEXT pin. I recommend dividing the voltage by half, as the minimum is only 4.7V

  • Lowering the VCCEXT voltage also greatly reduces the IC’s internal power dissipation

Net Naming (Farris)

Wiring and Connections (Farris)

Component Labels (Farris)

Design-for-Test (Farris)