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Also, UART’s serial communication has a special bit called parity bit. Parity bit is a simple error checking bit that saves whether the data is even or odd at the transmitter, and checks if the data is still even or odd at the receiver, in case the data bit is distorted due to noises.

1 bit

Start

5-9 bits

Data

0-1 bit

Parity

1-2 bits

Stop

Pros and Cons

Pros	Cons
Parity bit supports error checking Only 2 wires are used without clock Very common and universal data can be customized between 5-9 bits	Maximum data frame for each packet is limited to 9 1:1 communication only Baud rate must be consistent within 10% tolerance

SPI - Serial Peripheral Interface

Synchronous full-duplex communication protocol that allows a single master with multiple slaves
It uses 3 basic signal lines, SCK (Clock), MOSI (Master output -> slave input), MISO (Master input <- slave output), along with SS/CS (slave select or chip select) line.
The master device would have as many SS/CS lines as there are slaves connected to the master. In SPI, SCK & SS lines are controlled by the master to choose which slave device to communicate with and what to do with that slave device.
By pulling the SS line of the desired slave device low, master device initiates communication with the selected slave device.
Data signal is simple and continuous logic high’s and low’s.

Pros and Cons

Pros	Cons
Slave selecting is very simple Higher data transfer rate due to wider bandwidth Separate MOSI and MISO lines allowing full duplex function No start and stop bits, continuous transfer of data allowed	Only one master Uses 3 + n wires, which can become problematic with more slaves No ACK bit to check a successful transfer of data (will be discussed in I2C section) No error checking bit like UART

I2C - Inter-Integrated Circuit

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ACK/NACK: after address frame and each data frame, the slave is given control over SDA line for one bit, so that it can pull the 9th bit down to low in order to indicate that data was successfully received by the slave. If the ACK bit is left high (also known as NACK state), master device can infer the data transfer was unsuccessful.

Start Condition

Address

7 bits

Read/Write

1 bit

ACK/NACK

1 bit

Data

8 bits

ACK/NACK

1 bit

Repeated Start

More Data & ACK/NACK bits

Stop

Condition

Pros and Cons

Pros	Cons
Only two lines needed to communicate Multiple masters and slaves ACK/NACK checking	Devices must take turns to communicate Masters cannot communicate directly with each other Smaller bandwidth

Hardware Configurations: Push-pull vs. Open drain

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Also, CAN, as it is an asynchronous communication protocol, requires transceivers on both receiving and transmitting sides of the signal.

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PROTOCOLS: UART - I2C - SPI - Serial communications

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